Let's get complicated.
I like to make things way more complicated than I need to.
Why?
I have no idea.
I'm a scientist, right? That's what they tell me, a food scientist, but a scientist none the less.
So I KNOW to do testing with as few variables as possible.
Right?
Apparently not.
I know my LCD works on the NEON Sunrise. I do not know that my serial interface works.
So I should test them separately, right?
No, not me. I'll test the serial by sending it's output to the LCD, because that seems like it would be easy, right?
https://www.youtube.com/watch?v=o52nzE9LuuA
So the 6522 VIA chip is in address space $6000-$7FFF, even though it only needs 16 address spaces. I figured I could jam the 6551 ACIA into the space as well, using $6800-$6803, the four address spaces it needs. And honestly, I've already shrunk the 32K RAM down to 16K, so I really have all the space from $4000 - $7FFF to work with. But I like being efficient.
Look, we found a problem. 🤦♂️
See that problem? The VIA would be active every time we accessed the ACIA. What am I saying would be.... IT WAS. In fact so much so, that trying to read the Data Received Register in the ACIA caused bus contention with the VIA which was trying to output the contents of Register B. And the contents of that register were generally zero, so it drove everything down. The CPU could never get a good reading and would just come back with either $00 or more often $01.
Writing worked, because both would just accept the data, the ACIA sending it over the serial line, and the PB0-7 lines. Which really did nothing, because they're only hooked up to the LCD, and without also sending the enable signal on Port A, the LCD ignored it.
So now there's some additional logic. I did it in the breadboard with all four gates of NAND logic on a 4LS00, but since I have both AND and NOT gates on the PCB with unused gates now, I can add it without adding any new logic chips.
You saw in the video that I broke the trace to Pin 22 (Output Enable) on the SRAM. That in the end, wound up doing absolutely nothing. I ran it off to an OR gate to combine A14 OR A15, which didn't change it's functionality at all. If I followed my own logic as I was talking, I would have needed to break the trace to Pin 20 (Chip Enable) and insert that logic. Since it started working after that, I thought I did it right.
That all followed from trying to make sense of the datasheet, which only ever shows high impedance when Chip Enable is high. But disabling output would do the same thing.
But to reiterate what I said in the video, I probably didn't need to do that, as the bus contention was actually from the VIA. So I may not update the schematic.
As I continue to work on the glue logic for this, I think more and more about using programmable logic, like GALs. I did order a few when I placed my last order with Jameco, but I haven't learned how to use program them yet. That may be a segment in it's own right.
One thing I'd like to start doing as we move forward, is building a community around this project. Not in the development of it yet, as I want to get the basics down and the 65816, Keyboard input, VGA output, and Serial terminal working first. But get people thinking about it. I think that's starting with the people who comment on the videos and the conversations we're having.
One thing I'd like to start looking at is case designs. Should it include the keyboard? And how many SNES ports? (Yes, I have decided that we're using the SNES controllers, they're my favorite.) I want to do expansion cards, but how? Or do we do multiple case designs like the Amiga did?
What do you think?